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CSP TVS Flip Chip TVS Diode Array
PROTECTION PRODUCTS Description
The SFC05-4 is a quad flip chip CSP TVS diode array. They are state-of-the-art devices that utilize solid-state silicon-avalanche technology for superior clamping performance and DC electrical characteristics. The SFC series TVS diodes are designed to protect sensitive semiconductor components from damage or latchup due to electrostatic discharge (ESD) and other voltage induced transient events. The SFC05-4 is a 6-bump, 0.5mm pitch flip chip array with a 3x2 bump grid. It measures 1.5 x 1.0 x 0.65mm. This small outline makes the SFC05-4 especially well suited for portable applications. CSP TVS devices are compatible with current pick and place equipment and assembly methods. Each device will protect up to four data or I/O lines. The CSP design results in lower inductance, virtually eliminating voltage overshoot due to leads and interconnecting bond wires. They may be used to meet the ESD immunity requirements of IEC 61000-4-2, Level 4 (15kV air, 8kV contact discharge).
SFC05-4
PRELIMINARY
Features
u 300 Watts peak pulse power (tp = 8/20s) u Transient protection for data lines to
IEC 61000-4-2 (ESD) 15kV (air), 8kV (contact) IEC 61000-4-4 (EFT) 40A (5/50ns) IEC 61000-4-5 (Lightning) 24A (8/20s) Small chip scale package requires less board space Low profile (< 0.65mm) No need for underfill material Protects four I/O or data lines Low clamping voltage Working voltage: 5V Solid-state silicon-avalanche technology
u u u u u u u
Mechanical Characteristics
u JEDEC MO-211, Variation BB, 0.50 mm Pitch Chip u Marking : Marking Code u Packaging : Tape and Reel
Scale Package (CSP)
Applications
u u u u u u u u
Cell Phone Handsets and Accessories Personal Digital Assistants (PDAs) Notebook & Hand Held Computers Portable Instrumentation Pagers Smart Cards MP3 Players GPS
Device Dimensions
1.50
Schematic & PIN Configuration
B
1.00
0.50
0.50 TYP
0.65 0.150
A 1 2 3
SFC05-4 Maximum Dimensions (mm)
3 x 2 Grid CSP TVS (Bottom View)
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Revision 12/18/2000
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SFC05-4
PROTECTION PRODUCTS Absolute Maximum Rating
R ating Peak Pulse Pow er (tp = 8/20ms) Peak Pulse Current (tp = 8/20ms) ESD p er IEC 61000-4-2 (Air) ESD p er IEC 61000-4-2 (Contact) Soldering Temp erature Op erating Temp erature Storage Temp erature Symbo l Pp k I PP V ESD TL TJ TSTG Value 300 24 >25 >15 260 (10 seconds) -55 to +125 -55 to +150
PRELIMINARY
Units Watts A kV
o
C C C
o
o
Electrical Characteristics
SFC05-4 fo r 5V Line s Par ame te r Reverse Stand-Off Voltage Reverse Breakdow n Voltage Reverse Leakage Current Clamp ing Voltage Clamp ing Voltage Junction Cap acitance Symbo l V RWM V BR IR VC VC Cj It = 1mA VRWM = 5V, T=25C IPP = 5A, tp = 8/20s IPP = 24A, tp = 8/20s VR = 0V, f = 1MHz 6 10 9.5 11 350 Co nd itio ns Minimum Typ ical Maximum 5 Units V V A V V pF
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SFC05-4
PROTECTION PRODUCTS Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
10
110
PRELIMINARY
Power Derating Curve
Peak Pulse Power - PPP (kW)
100 % of Rated Power or IPP 90 80 70 60 50 40 30 20 10
1
0.1
0.01 0.1 1 10 Pulse Duration - tp ( s) 100 1000
0 0 25 50 75 100 125 150 Ambient Temperature - TA (oC)
Pulse Waveform
110 100 90 80 Percent of IPP 70 60 50 40 30 20 10 0 0 5 10 15 Time (s) 20 25 30 td = IPP/2 e
-t
Clamping Voltage vs. Peak Pulse Current
10.00
Waveform Parameters: tr = 8s td = 20s
9.00 Clamping Voltage - Vc (V) 8.00 7.00 6.00 5.00 4.00 3.00 2.00 1.00 0.00 0 5 10 15 20 25 30 Peak Pulse Current - Ipp (A) Waveform Parameters: tr = 8s td = 20s
ESD Clamping (8kV Contact Discharge)
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SFC05-4
PROTECTION PRODUCTS Applications Information
Device Connection Options The SFC05-4 has solder bumps located in a 3 x 2 matrix layout on the active side of the device. The bumps are designated by the numbers 1 - 3 along the horizontal axis and letters A - B along the vertical axis. The lines to be protected are connected at bumps A1, B1, A3, and B3. Bumps A2 & B2 are connected to ground. All path lengths should be kept as short as possible to minimize the effects of parasitic inductance in the board traces. Wafer Level CSP TVS CSP TVS devices are wafer level chip scale packages. They eliminate external plastic packages and leads and thus result in a significant board space savings. Manufacturing costs are minimized since they do not require an intermediate level interconnect or interposer layer for reliable operation. They are compatible with current pick and place equipment further reducing manufacturing costs. Certain precautions and design considerations have to be observed however for maximum solder joint reliability. These include solder pad definition, board finish, and assembly parameters. Printed Circuit Board Mounting Non-solder mask defined (NSMD) land patterns are recommended for mounting the SFC05-4. Solder mask defined (SMD) pads produce stress points near the solder mask on the PCB side that can result in solder joint cracking when exposed to extreme fatigue conditions. The recommended pad size is 0.200 10 mm with a solder mask opening of 0.350 0.025 mm. Grid Courtyard The recommended grid placement courtyard is 1.3 x 1.8 mm. The grid courtyard is intended to encompass the land pattern and the component body that is centered in the land pattern. When placing parts on a PCB, the highest recommended density is when one courtyard touches another.
To Connector
PRELIMINARY
Device Schematic & Pin Configuration
B
A 1 2 3
Layout Example
To Protected IC Ground To Protected IC
NSMD Package Footprint
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SFC05-4
PROTECTION PRODUCTS Applications Information (Continued)
Printed Circuit Board Finish A uniform board finish is critical for good assembly yield. Two finishes that provide uniform surface coatings are immersion nickel gold and organic surface protectant (OSP). A non-uniform finish such as hot air solder leveling (HASL) can lead to mounting problems and should be avoided. Stencil Design A properly designed stencil is key to achieving adequate solder volume without compromising assembly yields. A 0.100mm thick, laser cut, electro-polished stencil with 0.275mm square apertures and rounded corners is recommended. Reflow Profile The flip chip TVS can be assembled using standard SMT reflow processes. As with any component, thermal profiles at specific board locations can vary & must be determined by the manufacturer. The flip chip TVS peak reflow temperature is 230 10 C, but the device can withstand up to 260 C peak reflow temperature. Time above eutectic temperature (183 C) should be 50 10 seconds. During reflow, the component self-aligns itself on the pad. Circuit Board Layout Recommendations for Suppression of ESD Good circuit board layout is critical for the suppression of ESD induced transients. The following guidelines are recommended:
l l l l l l
PRELIMINARY
Stencil Design
Reflow Profile
Place the TVS near the input terminals or connectors to restrict transient coupling. Minimize the path length between the TVS and the protected line. Minimize all conductive loops including power and ground loops. The ESD transient return path to ground should be kept as short as possible. Never run critical signals near board edges. Use ground planes whenever possible.
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SFC05-4
PROTECTION PRODUCTS Outline Drawing - SFC05-4 PRELIMINARY
Land Pattern - SFC05-4
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SFC05-4
PROTECTION PRODUCTS Marking Codes
Par t Numbe r SFC05-4 Mar king Co d e F45U
PRELIMINARY
Ordering Information
P ar t Numbe r SFC05-4.TM Wo r king Vo ltage 5V Qty p e r Reel 6,000 R e e l Size 7 Inch
Contact Information
Semtech Corporation Protection Products Division 652 Mitchell Rd., Newbury Park, CA 91320 Phone: (805)498-2111 FAX (805)498-3804
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